RISC-V Steel Hardware Docs

Introduction

RISC-V Steel is a microcontroller design developed in Verilog that implements the RV32I instruction set of RISC-V. It is designed for easy, seamless integration into embedded systems, systems-on-chip (SoC), and FPGA designs, facilitating the rapid development of innovative RISC-V applications.

RISC-V Steel can run real-time operating systems such as FreeRTOS, as well as bare-metal embedded software. Its design includes components such as memory, timers, and interfaces for UART, GPIO, and SPI communication, enabling RISC-V Steel to integrate with a variety of sensors and actuators commonly used in embedded applications.

For information on how to develop new applications with RISC-V Steel, see the User Guide.

RISC-V Steel implements the following features of the RISC-V specifications:

• the RV32I Base Integer Instruction Set, v2.1
• the Zicsr Extension for Control and Status Register (CSR) Instructions, v2.0
• the Machine-Level ISA, v1.13

Architecture

A top-level view of RISC-V Steel architecture is presented in the diagram below.

Figure 1. RISC-V Steel Architecture

Source Files

The source files of RISC-V Steel are saved in the hardware/ folder of its GitHub repository.

Configuration

The table below lists the configuration parameters of RISC-V Steel Top Module, rvsteel.v:

Parameter name and description	Value type	Default value
BOOT_ADDRESS Memory address of the first instruction to be fetched and executed.	32-bit hexadecimal	32'h00000000
CLOCK_FREQUENCY Frequency (in Hertz) of the clock input signal.	Integer	50000000
UART_BAUD_RATE Baud rate of the UART module (in bauds per second).	Integer	9600
MEMORY_SIZE Size of the memory module (in bytes).	Integer	8192
MEMORY_INIT_FILE Absolute path to the memory initialization file.	String	(empty string)
GPIO_WIDTH Number of general-purpose I/O pins.	Integer	1
SPI_NUM_CHIP_SELECT Number of Chip Select (CS) lines for the SPI Controller.	Integer	1

I/O Signals

The input/output signals of RISC-V Steel Top Module, rvsteel.v, are listed in the table below:

Pin name and description	Direction	Size
clock Clock input.	Input	1 bit
reset Reset pin (active-high).	Input	1 bit
halt Halt pin (active-high).	Input	1 bit
uart_rx UART receiver pin.	Input	1 bit
uart_tx UART transmitter pin.	Output	1 bit
gpio_input GPIO input signals.	Input	GPIO_WIDTH
gpio_oe GPIO output enable.	Output	GPIO_WIDTH
gpio_output GPIO output signals.	Output	GPIO_WIDTH
sclk SPI Controller clock.	Output	1 bit
pico SPI Peripheral In Controller Out.	Output	1 bit
poci SPI Peripheral Out Controller In.	Input	1 bit
cs SPI Chip Select lines.	Output	SPI_NUM_CHIP_SELECT

Memory Map

The devices in RISC-V Steel are mapped to memory addresses as detailed below:

Start address	Final address	Range size (Bytes)	Device
0x00000000	0x(MEMORY_SIZE-1)	MEMORY_SIZE	RAM
0x80000000	0x8000000f	16	UART Controller
0x80010000	0x8001001f	32	Timer
0x80020000	0x8002001f	32	GPIO Controller
0x80030000	0x8003001f	32	SPI Controller